Double-data rate Third-generation (DDR3) main memory technologies are developed by the Joint Electronic Devices Engineering Council (JEDEC) for use in servers, workstations, and high-performance portable applications that require deep memory.
Nexus Technology offers high quality and high fidelity interposers, enabling the industry to confidently and accurately gain access to DDR3 main memory buses for debug and compliance verification. …
DDR3 main memory is available in standard Ball-Grid-Array (BGA) component packages as well as dual-inline-memory-modules of DIMM and SODIMM. Standard BGA packages are soldered directly to the printed circuit board (PCB) while modules comprise a series of packages in a standard PCB format with standard connections between the DIMM and the main board. Interposers are available for both component packages and DIMM and SODIMM modules.
|240 Pin DIMM||✓||✓||✓|
|240 Pin DIMM||*||✓||*|
|204 Pin SODIMM||✓||✓||✓|
|204 Pin 72 Bit SODIMM||*||✓||*|
|244 Pin MINIDIMM||*||✓||*|
|Package||EdgeProbe™||Direct Attach||Socketed||Socketed||Riser||Component Socket|
|78 Ball x4/x8||✓||✓||✓||✓||Yes||Yes|
|96 Ball x16||✓||✓||✓||✓||Yes||Yes|
|Custom||Custom designs are also available. Please contact us.|
*If you don’t see what you need, please contact us for the most up to date information.
Electrical analysis is enabled by using either an EdgeProbe, High Density, or Socketed interposer to capture memory activity on an oscilloscope. The oscilloscope is then used to debug, analyze, and verify the analog characteristics of your design. Presenting an accurate representation of the signals under test to the oscilloscope is critical. Nexus interposers provide an unobtrusive interconnect and accurate signal to your oscilloscope.
Logic analysis is performed using a logic / compliance interposer to capture memory activity on a logic or memory analyzer. The logic or memory analyzer is then used to debug, analyze, and verify the logic (basic protocol) of your design. Compliance analysis uses the same interposers to capture activity on a memory analyzer. The memory analyzer is then used to debug, analyze, margin test, performance analyze, and verify the memory protocol.