Low power double-data rate fifth-generation (LPDDR5) mobile memory technologies are developed by the Joint Electronic Devices Engineering Council (JEDEC) for use in handheld devices or applications where low-power and small size is critical. Nexus Technology offers high quality and high fidelity interposers, enabling the industry to confidently and accurately gain access to LPDDR5 mobile memory buses for debug and compliance verification...
LPDDR5 mobile memory is available in standard Ball-Grid-Array (BGA) component packages. Standard BGA packages are soldered directly to the printed circuit board (PCB). Interposers are available for component packages detailed below:
|Package (ChxDb)||EdgeProbe™||Direct Attach||Logic Compliance||Riser||Component Socket|
|315 Ball (2×16)||✓(XH)||✓(XH)||✓||Yes||No|
|496 Ball (4×16)||*||✓(XH)||✓||Yes||No|
|Custom||Custom designs are also available. Please contact us.|
* If you don’t see what you need, please contact us for the most up to date information.
Nexus Technology’s XH Series interposers bring new enhancements to the EdgeProbe™ and Direct Attach types of memory component interposers that maintain signal integrity across the interposer path as well as provide for extremely high-fidelity oscilloscope probe points for both leading edge and emerging memory technologies.
Electrical analysis is enabled by using either an EdgeProbe, High Density, or Socketed interposer to capture memory activity on an oscilloscope. The oscilloscope is then used to debug, analyze, and verify the analog characteristics of your design. Presenting an accurate representation of the signals under test to the oscilloscope is critical. Nexus interposers provide an unobtrusive interconnect and accurate signal to your oscilloscope.
Logic analysis is performed using a logic / compliance interposer to capture memory activity on a logic or memory analyzer. The logic or memory analyzer is then used to debug, analyze, and verify the logic (basic protocol) of your design. Compliance analysis uses the same interposers to capture activity on a memory analyzer. The memory analyzer is then used to debug, analyze, margin test, performance analyze, and verify the memory protocol.